(a) Field of the present invention
The present invention relates to a serial bus controller used in a microcomputer-applied device for controlling a serial communication bus connected to a plurality of microcomputer-applied devices, any of which is a candidate for the master device on the serial communication bus.
(b) Description of the Related Art
Recently, as a higher level is achieved in the function and performance of the microcomputer-applied devices, the volume of data to be communicated between microcomputer-applied devices, or computer stations, has been increased. This tendency highlights the importance of the performance in data communication between the microcomputer-applied devices, which includes a higher reliability in data communication as well as a higher speed.
Any of the microcomputer-applied devices of this sort itself can be a candidate for the master device on the serial communication bus which plays a leading role in the data communication during a certain interval. In a data communication system including a plurality of such candidates on a single serial communication bus, it is not clear which candidate is the master device and which are the slave devices, proper data communication cannot be normally achieved. When a plurality of candidates for the master device simultaneously start communication as the master device, competition takes place among the candidates. In such a circumstance, there is a scheme in the system for selecting one of the candidates as the sole master device by utilizing the interference between the data thus transmitted, which eventually specifies one or more losers in the competition.
The losers in the competition are requested to release the serial communication bus immediately upon losing the competition, and not to interfere with the communication effected by the winner in the competition, or master device. Besides, the loser must perform an after-treatment for the failed communication which becomes due as a result of the lost competition, as well as preparation procedures as a slave device possibly assigned by the master device.
FIG. 1 is a block-diagram showing a conventional serial bus controller in a computer station. The conventional serial bus controller 10 for controlling data communication through a serial communication bus 17 comprises a competition result discriminator 11 and a serial communication section 12. The competition result discriminator 11 compares a clock signal SCK and the contents of data SDA appearing on the serial communication bus 17 against a clock signal CKO and the contents of data DAO, respectively, output from the serial communication section 12 of the own station, to supply a lost competition/interrupt demand signal INTD to a CPU (not shown in the drawing) when the lost competition is detected as a result of the comparison.
The serial communication section 12 comprises a communication controller 13 for controlling the communication through the serial communication bus 17, and generates an end-of-communication/interrupt demand signal INTE after performing normal serial communication procedures. A CPU bus 15 connects the serial bus controller 10 with the CPU.multidot. for data transmission, whereas an internal bus 16 connects the serial control section 12 with the CPU bus 15. The communication controller 31 comprises a bus release controller 31 and a slave mode setting section 32.
With reference to FIG. 2 showing a time-chart of the conventional serial bus controller 10, according to FIG. 1, an example of operations of the conventional serial bus controller 10 will be described, in the event of competition among a plurality of candidates for the master device on the communication bus.
Assume that the serial bus controller 10 of FIG. 1 is in the state of serial data communication (state "M" in FIG. 2), to thereby reveal the own station as one of the candidates for the master device. The competition result discriminator 11 receives the clock signal SCK and the contents of data SDA appearing on the serial communication bus 17, to compare the clock signal SCK and the contents of data SDA with the clock signal CKO and the contents of data DAO, respectively, which are to be output from the own station. The occurrence of the lost competition is decided as a result of the comparison if any difference is recognized in the comparison, and the lost competition/interrupt demand signal INTD is output from the serial communication section 12.
During processing the lost competition interrupt procedures which become due as a result of the lost competition, the CPU provides a command through the internal bus 16 to the bus release controller 31 to halt the output of the clock signal CKO and data DAO from the own station, thereby releasing the communication bus 17 in the procedure "B" in FIG. 2 in order not to interfere with the communication made from the master device, or winner in the competition. Further, the CPU performs an after-treatment for the failed communication which is due as a result of the lost competition, and provides a command to the slave mode setting section 32 to perform communication preparation procedures for a slave device ("C" in FIG. 2) which may be possibly assigned by the master device.
On the other hand, if the communication by the serial bus controller 10 is finished properly as a result of winning in the competition, the serial communication section 12 outputs the end-of-communication/interrupt demand signal INTE, and the CPU provides a command to the serial bus controller 10 to perform end-of-communication procedures ("D" in FIG. 2) including communication preparation procedures for a slave device which may be possibly assigned by the master device, and to perform preparation procedures for the next communication.
After finishing the above procedures, the serial bus controller 10 which is either in the state of the slave device or in the state of master device moves into an idling state ("RY" in FIG. 2). After the idling state "RY" as a slave device, the serial bus controller 10 works in the state of the master device "M" if the state of the slave device is restored to the state of the master device, or works in the state of slave device "S" if the serial bus controller 10 is assigned as such ("M/S" in FIG. 2). Before arrival at the waiting state "RY" after the lost competition, the serial bus controller 10 must pass through a communication disabled state "V" in FIG. 2, which fact may cause the serial bus controller 10 to delay in responding to a possible assignment for a slave device made by the master device.
As described above, the serial bus controller performs releasing the serial bus and preparation for a slave device in interrupt procedures after detecting the lost competition. In this procedures, the release of the serial bus is sometimes delayed depending on the program processing speed of the CPU or the state of the serial communication bus. Such a delay of the preparation procedures for the slave device and the release of the serial bus causes troubles against the communication from the master device in the serial communication system.